O. Bazangani, P.A. Eliasi, S. Picek, I. Buhan, L. Batina
2024 Design, Automation & Test in Europe Conference (DATE 2024)

Summary: Side-channel attacks cause a significant threat to security implementations in embedded devices. An automated framework simulating side-channel behaviours can offer invaluable insights into leakage origins and characteristics, helping developers improve those devices during the design phase. While there has been substantial effort towards crafting leakage simulators, earlier methods either necessitated significant manual work for reverse engineering the micro-architectural layer or depended on Deep Learning approaches without interpretable insights into the leakage source. This work investigates whether machine learning can learn pipeline leakage characteristics of ARM Cortex-M processors, advancing automated and interpretable side-channel leakage simulation.

Summary: Mitigating side-channel leakage in cryptographic components is a vital concern for developers working with embedded devices. The conventional side-channel analysis demands substantial man- ual effort for setup preparation and trace recording, rendering it more intricate during the dynamic design phase, where software alterations occur frequently. Additionally, identifying the specific instruction(s) responsible for leakage has been hindered by limited hardware descriptions and restricted access to process technology information. We introduce ABBY, an open-source side-channel leakage profil- ing framework that targets the microarchitectural layer. Existing solutions to characterize the microarchitectural layer are device- specific and/or require extensive manual effort. ABBY’s main inno- vation is data collection, which can then automatically characterize the microarchitectural behaviour of a target device and has the additional benefit of being extendable to other similar devices. Using ABBY, we created two datasets that capture the interaction of instructions for the ARM CORTEX-M0/M3 architecture. These sets are the first to capture detailed information on the microarchi- tectural layer. They can be used to explore various leakage models suitable for creating side-channel leakage simulators. A prelim- inary evaluation of a leakage model produced with our dataset of real-world cryptographic implementations shows performance comparable to state-of-the-art leakage simulators.